In many applications, the op-amp DC gain requirement is higher than what is achievable with simple single stage single stage topologies. Techniques to enhance the op-amp DC gain without going into multiple stage architecture are especially welcome in high speed circuits, where the high current levels make the transistor large.
A very widely-used method is shown in FIG. 1. In FIG. 1, the gate of the cascode transistor M2 is connected to the output of the feedback stage Al. This has two effects: 1) the resistance at the node NC is lowered by the loop gain Al and bandwidth increased, and 2) the total output conductance of the current source is lowered by the same amount. A calculation using equivalent MOSFET circuits yields a total output conductance:gout=(gds1gds2)/A1 gm2Thus, the regulation lowered the output conductance by the gain of the regulation amplifier Al and, when the current source is utilized in an operational transconductance amplifier (OTA) the DC gain is increased by the same amount.
Referring now to FIGS. 2A-2C, three different implementations of the regulation amplifier are shown. While all three regulation amplifiers work, they each have certain drawbacks. In FIG. 2A the regulation amplifier is a simple design but sets the voltage on the cascode node NC unnecessarily high. The circuit in FIG. 2B utilizes a level shifter. To set the voltage on the cascode node NC above Vdsat1, Vdsat4 needs to be higher than Vdsat1+Vdsat3. The large value of Vdsat4 degrades gm4, so as to the loop gain and bandwidth. The other implementation in FIG. 2C is a common gate amplifier. The low input impedance largely reduces the loop gain and output impedance, and makes it inferior to the circuit in FIG. 2A, although it allows the biasing of the cascade node NC to a lower voltage.
Therefore, it would be desirable to provide a regulation amplifier that overcomes the above problems. The regulation amplifier would use a wide-band wide-swing CMOS gain enhancement technique.